This invention relates generally to dual stage amplifiers, and more particularly to a dual stage amplifier with a clamp circuit for preventing overcharge in a compensation capacitor.
Dual stage amplifier circuits are used in a variety of applications. Such circuits may include a differential input first amplifier stage with a second stage having an output related to the difference between the terminals of the first amplifier stage. A compensation capacitor is sometimes employed between the input and output of the second amplifier stage, in order to compensate for instability in the dual stage circuit. The size of such a compensation capacitor may be varied according to the desired frequency response characteristics of the circuit. Thus, where the bandwidth of the dual stage amplifier needs to be reduced, the compensation capacitor may be relatively large. For example, where a dual stage amplifier is used as an error amplifier in a switching regulator, it may be desirable to reduce the dual stage error amplifier bandwidth below the switching frequency of the switching regulator.
In addition to stability, the response time of the output may be an important performance characteristic of a dual stage amplifier. Where a compensation capacitor is employed between the input and output of the second amplifier stage, overcharging of the compensation capacitor may lead to unacceptably long output response times in the dual stage amplifier as well as undesirable overshoot in the output of a switching regulator or other closed loop system in which the dual stage amplifier is employed as an error amplifier. Such overcharging of the compensation capacitor may occur when the differential input terminals are imbalanced, such as during power up when the terminals are in indeterminate states. For example, in a switching regulator, a dual stage error amplifier may have a positive differential input terminal connected to a reference voltage source, and a negative differential input terminal connected to the regulated output through a resistive voltage divider network. Due to internal timing of the switching regulator, the reference voltage source may rise to its steady state voltage faster than does the regulated output. Thus, an imbalance occurs at the differential inputs, where the positive terminal is at the reference voltage and the negative terminal is near zero volts.
Such an imbalance at the dual stage amplifier inputs may cause the second stage input to go to one of the power supply rails or to ground in a single-ended configuration. Where the second amplifier stage is an inverter, such as a MOS transistor with a drain connected to the error amplifier output and a gate connected to the second stage input, the compensation capacitor may be connected in a feedback path between the drain and gate of the transistor. Excessive charging of the compensation capacitor may thus occur where an input imbalance condition causes the second stage input to go to ground or a supply rail. When the input imbalance condition is removed, the discharging of the compensation capacitor may lead to excessive dual stage amplifier output response time and/or closed loop system overshoot, particularly where the compensation capacitor is large. Accordingly, there exists a need for improved apparatus and methods by which dual stage amplifier output response time and system overshoot may be reduced or eliminated.
The present invention provides a dual stage amplifier with a clamping circuit and a methodology which minimize or overcome the above mentioned shortcomings, along with a clamping circuit for use with a dual stage amplifier. The invention may be employed in order to reduce the overcharging of a compensation capacitor in such a dual stage amplifier, however, the invention finds utility and may be advantageously employed in other applications.
According to one aspect of the present invention, there is provided a dual stage amplifier, comprising a first amplifier stage with a first input and a first output, a second amplifier stage having a second output and a second input operatively connected to the first stage output. The amplifier further includes a compensation capacitor in electrical communication with the second stage input and the second stage output, and a clamping circuit in electrical communication with the second stage, wherein the clamping circuit is adapted to prevent overcharging of the compensation capacitor. The clamping circuit may include a low vgs clamp, a high vgs clamp, and/or a combination low vgs and high vgs clamp, wherein the low vgs clamp is adapted to counteract a drop in the second stage input voltage, and the high vgs clamp is adapted to counteract a rise in the second stage input voltage.
According to another aspect of the invention, the low vgs clamp may sense a voltage drop at the second stage input and inject current from a positive supply into the second stage input to counteract the sensed voltage drop, whereby overcharging of the compensation capacitor is reduced. In this regard, the second amplifier stage may include a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the output transistor is adapted to control the second stage output according to the second stage input, for example, in an inverter amplifier configuration. In this case, the low vgs clamp may comprise a first switching component, such as an NMOS transistor, operatively connected to the gate of the output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage.
In addition, the low vgs clamp may include a second switching component, such as a PMOS transistor, operatively connected to the positive supply and the first switching component which selectively provides current to the gate of the output transistor according to the signal from the first switching component. In this manner, the current provided by the second switching device to the gate of the output transistor counteracts a voltage drop at the second stage input. Thus, in an inverter type second stage, the sourcing of current to counteract a drop in the second stage input effectively reduces the amount or likelihood of overcharging of a compensation capacitor operatively connected in a feedback path between the second stage input and the second stage output. The clamping circuit may be further adapted to activate the provision of current when the voltage at the second stage input has reached a certain trip point or value, allowing for normal amplifier operation above such a value. For example, the trip point on the low vgs clamp may be advantageously set above the threshold voltage of the second stage MOS transistor, in order to ensure operation of the clamp circuit prior to the second stage transistor shutting off.
Where the clamping circuit includes a high vgs clamp, alone or in combination with a low vgs clamp, the high vgs clamp may also prevent or minimize overcharging of the compensation capacitor. Toward this end, the clamp may be adapted to sense a voltage rise at the second stage input and to sink current to the negative supply from the second stage input to counteract the sensed voltage rise, whereby the possibility of overcharging the compensation capacitor is reduced.
For example, where the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output in an inverter configuration, the high vgs clamp may comprise a first switching component operatively connected to the gate of the output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage. A second switching component operatively connected to the negative supply and the first switching component then selectively sinks current from the gate of the output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the output transistor counteracts a voltage rise at the second stage input.
In such a high vgs clamp, the first switching component may comprise, for example, an NMOS transistor with a gate connected to the second stage input, and the second switching component may include an NMOS transistor connected to the second stage input, so as to sink current from the second stage input to counteract a voltage rise thereat, in accordance with a signal from the first switching component. The high vgs clamp may thus prevent or reduce overcharging of the compensation capacitor, thereby reducing the dual stage amplifier response time and system overshoot. In accordance with another aspect of the invention, the clamping circuit may include a high vgs clamp and/or a low vgs clamp, or a combination thereof, as needed or desired to account for anticipated or known input imbalance conditions, depending on the dual stage amplifier application and/or configuration.
According to still another aspect of the invention, there is provided a clamp circuit for clamping a second stage input in a dual stage amplifier having a first amplifier stage with a first input and a first output and a second amplifier stage with a second output and a second input operatively connected to the first output. The clamp circuit comprises means for sensing a voltage at the second stage input and providing a signal according to the sensed voltage, and means for selectively sourcing or sinking current to or from the second stage input, respectively, according to the signal. The means for sensing the voltage at the second stage input and providing a signal according to the sensed voltage may include a first switching component operatively connected to the second stage input and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage. In addition, the means for selectively sourcing or sinking current to the second stage input according to the signal may comprise a second switching component operatively connected the first switching component and one of a positive and a negative supply, which is adapted to selectively source or sink current to or from the second stage input, respectively, according to the signal from the first switching component.
Where, for example, the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output for controlling the second stage output according to the second stage input, the first switching component may be operatively connected to the gate of the output transistor and may accordingly sense a voltage at the second stage input and provide a signal according to the sensed voltage. In this regard, the second switching component may be operatively connected to a positive supply and the first switching component and may selectively provide current to the gate of the output transistor according to the signal from the first switching component.
In this manner, the current provided to the gate of the output transistor counteracts a voltage drop at the second stage input, thus preventing or minimizing the deleterious effects due to overcharging of a compensation capacitor connected from the second stage input to the second stage output. As another example, the second switching component may be operatively connected to a negative supply and the first switching component and adapted to selectively sink current from the gate of the output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the output transistor counteracts a voltage rise sensed by the first switching component at the second stage input.
In accordance with yet another aspect of the invention, there is provided a method of biasing the second stage input in a dual stage amplifier. The method comprises providing a first component in electrical communication with the second stage input, sensing a voltage at the second stage input using the first component, generating a signal using the first component according to the sensed voltage at the second stage input, providing a second component in electrical communication with the first component and the second stage input, and selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component.
The step of selectively biasing the second stage input may include selectively sourcing or sinking current to or from the second stage input, respectively, using the second component according to the signal from the first component. This may include, for example, selectively sourcing current to the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the negative supply, and/or selectively sinking current from the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the positive supply.
According to another aspect of the invention, where the method is employed in connection with a dual stage amplifier, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, the first component may be operatively connected to the gate of the output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage. In addition, the second component may be operatively connected to the positive or negative supply and the first switching component and adapted to selectively source or sink current to or from the gate of the output transistor, respectively, according to the signal from the first switching component. Thus, the methodology provides a current which is sourced to or sinked from the gate of the output transistor, which advantageously counteracts a voltage change at the second stage input, thereby minimizing or eliminating compensation capacitor overcharging.
According to yet another aspect of the invention, there is provided a method of preventing overcharging of a compensation capacitor in an amplifier circuit. The method includes sensing a node voltage associated with the compensation capacitor, determining whether the sensed node voltage is within a desired range, and providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range. For example, determining whether the sensed node voltage is within a desired range may comprise determining whether the sensed node voltage is greater than a desired maximum voltage. In addition, providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range may comprise sinking current from the node associated with the compensation capacitor if the sensed node voltage is greater than the desired maximum voltage.
Alternatively, or in combination, the step of determining whether the sensed node voltage is within a desired range may comprise determining whether the sensed node voltage is less than a desired minimum voltage, and the step of providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range may comprise sourcing current to the node associated with the compensation capacitor if the sensed node voltage is less than the desired minimum voltage.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.